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Contact Force and Temperature Effects on

Semiconductor Wafer Test Probes


Contact Force

In addition to these characteristics, there are other properties that affect overall test probe performance.  For example, it is important to establish and maintain good metal-to-metal contact during the mating of the test probe with the DUT. Very light contact force will result in unstable contact resistance and false negatives resulting in a low process yield.  Very high contact forces will produce stable CR values but can produce excessive wear scars and in the extreme case, can actually crack the wafer during the test.

The typical contact force for IC wafer test probes is on the order of 1-8 gf with a typical overdrive  (deflection after initial contact) in the range of 50-250 μm.  Some of the newer 3D configurations (Cu pillars or solder balls) require even tighter tolerances. The spring rate of a typical vertical probe is related to the physical geometry and elastic modulus of the probe material. The Young modulus of the Deringer-Ney probe alloys are similar and fall within a range of 17 to 19.6 x 106 psi (115 to 135 GPa).





IC wafer test probes must maintain stable properties at elevated temperatures.  In addition to the anticipated I²R heating of the wafer probe caused by the test currents, some wafer test protocols require heated chucks using temperatures in excess of 125°C. As noted earlier, IC manufacturers are on a never ending path to shrink the IC and reduce the pitch of the various features.  This produces very tightly packed test arrays on the wafer, resulting in probe cards that can exceed 10,000 individual test probes.  The heat generated by these tightly packed probes is challenging to dissipate and acts to raise the localised temperatures under test conditions. As a consequence, it’s important to maintain the mechanical strength of the test probes at temperatures significantly above the ambient temperature.  As shown in the graph below, the Deringer-Ney semiconductor alloys are mechanically stable at temperatures above 250°C.    



The semiconductor manufacturing process is complex and continues to be refined over time.  It’s been made possible and developed over many years by the fields of material science, quantum physics, optics, chemistry, engineering, and many other scientific disciplines.  Due to the ubiquity of the integrated circuit, little to no thought is given to these amazing devices by the average consumer as they find their way into everything from sophisticated smartphones to simple devices such as a $15 light dimmer switch. Worldwide, the end-product market using ICs exceeds $300B and will continue to grow for the foreseeable future.

Taking into account the market size, the demand for a low per-unit price, and the expensive infrastructure re-quired to make these devices, high production yield is essential in order for a manufacturer to survive.  As a consequence, every silicon die on every wafer will be tested as part of the fabrication process, followed by a final test performed after the die is mounted on a leadframe and packaged.  The earlier in the process a defective IC can be detected, the better.

During wafer testing, the only thing seperating the dies from the prober circuitry is the vast array of test probes. When designing contact probes for this type of application, many things need to be considered including probe material bulk resistance, contact force, number of test “touchdowns”, and current carrying capacity to name a few.  Deringer-Ney has years of experience in developing the materials and manufacturing the parts for this highly specialized application.  To learn more, contact one of our material scientists or application engineers.


Return to...High Performance Alloys for Semiconductor Test Applications 


[1] Bove R. Probe contactor having buckling beam probes. 3806801, 1974.

[2] Waldrop MM. The chips are down for Moore’s law. Nature. 2016 Feb 1; 530 (7589):144-7

[3] Daniels EB. ISMI Probe Council: Current Carrying Capability Measurement Standard.  In San Diego, CA, USA; 2009. 

[4] Kazmi R, Kilicaslan H, Hicklin J, Tunaboylu B. Measuring Current Carrying Capability (CCC) of Vertical Probes. In San Diego, CA, USA; 2010.

[5] Cassier A, Folwarski R, Kister J, Leong A. Determining Probe’s Maximum Allowable Current. In San Diego, CA, USA; 2015.


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